PRESS RELEASE

Contact:
Eric Seabrook
Aldec, Inc.
(702) 990-4400 ext. 224
erics@aldec.com

Verification Performance
Riviera IPT allows EDA departments to speed up design verification by a ratio of 100x or more over traditional RTL simulators. This performance increase virtually eliminates verification bottlenecks and speeds time-to-market from months to weeks. Riviera's simulation software comes with Alatek's patented Incremental Prototyping technology, which can accommodate memories, DSPs, ASICs and other devices, allowing joint verification of legacy designs, EDIF-based IP cores, existing hardware and HDL blocks. Such comprehensive coverage makes Riviera IPT the most universal design verification solution.

"Using the Incremental Prototyping technology with the versatility of Riviera's simulator makes for an unmatched combination of flexibility and performance," stated Eric Seabrook, Riviera Product Marketing Manager for Aldec.

Riviera IPT benefits from Alatek's Incremental Prototyping
The Incremental Prototyping technology from Alatek enables the designer to verify and optimize his or her design in manageable, smaller-sized blocks according to project schedules. Each block is simulated in software by the Design Verification Manager before being "pushed" into hardware. The hardware resident blocks remain "connected" with HDL blocks by the Design Verification Manager in software. Each newly tested HDL block is being "pushed" into hardware. In the end, most design blocks reside in the hardware and verification is performed in seconds instead of hours. Since testing requires only seconds, this allows designers to greatly increase the testbench coverage. This leads to enhanced design quality without traditional time penalties.

Price And Availability
Riviera IPT includes Alatek's Design Verification Manager, Library Manager, HDL Editor, Waveform Viewer, and the Aldec dual language simulation kernel. Two versions of IPT are available; v800 will accommodate 200k ASIC gates while the v2000 allows for 500k. The pricing for Riviera IPT dual language v2000 is $135,000 and is sold directly by Aldec and Insight Electronics LLC in the U.S. and authorized international distributors. Riviera IPT Beta versions will ship in May 2001. The deliveries of Riviera IPT will start in August 2001. For additional information about Riviera, go to www.aldec.com.

About Aldec

Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.